View PCA84C646_3199871.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

d a t a sh eet preliminary speci?cation supersedes data of june 1994 file under integrated circuits, ic14 1995 jun 15 integrated circuits PCA84C646; pca84c846 microcontrollers for tv tuning control and osd applications
1995 jun 15 2 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 contents 1 features 1.1 pcf84cxxxa kernel 1.2 vst and osd derivative 2 general description 3 ordering information 4 block diagram 5 pinning information 5.1 pinning 5.2 pin description 6 reset 6.1 reset trip level 6.2 reset status 7 analog control 7.1 6 and 7-bit pwm outputs (pwm00 to pwm07) 7.2 vst control 14-bit pwm dac 8 afc input 9 osd (on screen display) function 9.1 features 9.2 horizontal display position control 9.3 vertical display position control 9.4 clock generator 10 display ram organization 10.1 description of display ram codes 10.2 loading character data into display ram 10.3 writing character data to display ram 10.4 default value of the display character 11 character rom 11.1 character rom organization 12 osd control registers 12.1 derivative register 22 (con1) 12.2 derivative register 23 (con2) 12.3 derivative register 33 (con3) 12.4 derivative register 34 (con4) 12.5 derivative register 35 (vpos) 12.6 derivative register 36 (hpos) 12.7 derivative register 37 (bcc) 13 combination of two or more font cells to form a new font 14 osd clock in different tv standards 14.1 maximum number of characters per row 14.2 maximum number of rows per frame 15 t3: 8-bit counter 16 i 2 c-bus master slave transceiver 17 derivative registers 18 input/output 19 option lists 20 limiting values 21 dc characteristics 22 ac characteristics 23 afc characteristics 24 package outline 25 soldering 26 definitions 27 life support applications 28 purchase of philips i 2 c components
1995 jun 15 3 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 1 features 1.1 pcf84cxxxa kernel 8-bit cpu, rom, ram, i/o and derivative logic in one package over 80 instructions all instructions of 1 or 2 cycles quasi-bidirectional standard i/o port lines (p0, p1) configuration of i/o lines individually selected by mask external interrupt int/t0 2 direct testable inputs t0, t1 8-bit timer/event counter single level vectored interrupt: external ( int), counter/timer, i 2 c-bus and vsync configuration of optimal on-chip oscillator transconductance by mask on-chip oscillator clock frequency: 1 to 10 mhz power-on-reset and low-voltage detector low standby voltage and current in idle and stop modes single power supply: 4.5 to 5.5 v operating temperature: - 20 to +70 c. 1.2 vst and osd derivative 6 kbytes (PCA84C646) or 8 kbytes (pca84c846) system rom, 192 bytes system ram a multi-master i 2 c-bus interface one 14-bit pwm output for vst three afc inputs with 4-bit dac and comparator four 6-bit pwm and four 7-bit pwm outputs (dacs for analog controls) eight port lines with 10 ma led drive (at 1.2 v) capability programmable active level polarities of vsync/ hsync display ram: 64 10-bit display character fonts: 64 (62 customized + 2 special reserved codes) display starting position: 64 different positions by software control, both vertical and horizontal character size: 4 different character sizes, line-by-line basis, 1 dot = 1h/1v, 2h/2v, 3h/3v, 4h/4v. (h: osd clock period, v: number of horizontal scan line height) character matrix: 12 18 with no spacing between characters foreground colours: 8, character-by-character basis background colours: 8, word-by-word basis. available when background is either in north-west shadowing, box shadowing and frame shadowing mode background/shadowing modes: 4, no background, north-west shadowing, box shadowing, frame shadowing (raster blanking), frame basis on-chip oscillator for on screen display (osd) function character blinking rate: 1 : 1, 1 : 3, 3 : 1 (frequency: 1 16 , 1 32 , 1 64 or 1 128 of f vsync , programmable), character basis display format: flexible display format by using carriage return (cr) code spacing between lines: 4 different choices, from 0, 4, 8 or 12 horizontal scan lines auto display character ram address post increment when writing data on-chip power-on-reset vsync leading edge can generate interrupt (programmable enable/disable by software) 8-bit counter triggered by external pulse input.
1995 jun 15 4 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 2 general description the PCA84C646 and pca84c846 are 8-bit microcontrollers with enhanced osd and vst functions. the PCA84C646 and pca84c846 are members of the pca84c640 cmos microcontroller family. they include the pcf84cxxxa processor core, 6 or 8 kbytes of rom and 192 bytes of ram. i/o requirements are adequately catered for with 13 general purpose bidirectional i/o lines plus 16 function combined i/o lines. one 14-bit pwm analog control, 3 afc inputs (4-bit dac + comparator) for vst and four 6-bit and 7-bit pwm analog control outputs are provided. in addition to all these features a master-slave i 2 c-bus interface, 2 directly testable lines and an enhanced osd facility for flexible screen format (maximum of 64 character types) are also provided. the on-chip phase-locked loop (pll) oscillator for osd operation considerably reduces the radiation generated by the rc or lc oscillator. an 8-bit timer is integrated on-chip with a 5-bit prescaler. another 8-bit counter with schmitt-trigger input is used for clock/timer function application. figure 1 shows the block diagram of the PCA84C646 and pca84c846. 3 ordering information type number package name description version PCA84C646p sdip42 plastic shrink dual in-line package; 42 leads (600 mil) sot270-1 pca84c846p
1995 jun 15 5 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 4 block diagram handbook, full pagewidth pcf84cxxxa core excluding rom / ram 8-bit internal bus 8-bit timer / event counter cpu parallel i / o ports 8-bit counter rom 6 kbytes or 8 kbytes 4 x 6-bit pwm 4 x 7-bit pwm afc 3 x 4-bit dac + comparator i c-bus interface 2 on screen display 4 p00 to p07 p10 to p12 p14 dp00/pwm00 to dp07/pwm07 dp10 to dp13 dp20 to dp23 vob vow0 vow1 vow2 c vsync hsync test / emu xtal1 (in) xtal2 (out) reset 14-bit dac ram 192 bytes tdac afc0 to afc2 sda scl med169 t1 int / t0 t3 8-bit i/o ports 4 8 4 8 3 8 (1) (2) fig.1 block diagram rom size: (1) 6 kbytes for PCA84C646. (2) 8 kbytes for pca84c846.
1995 jun 15 6 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 5 pinning information 5.1 pinning fig.2 pin configuration PCA84C646p and pca84c846p (sdip42; sot270-1). handbook, halfpage 1 2 3 4 5 6 7 8 9 10 11 12 13 40 39 38 37 36 35 34 33 32 31 30 29 28 27 14 15 16 17 18 19 20 22 23 24 25 26 21 42 41 pca84c846 PCA84C646 vob vow2 dp22/vow1 dp23/vow0 p10/dxwr p11/dxrd dp13/tdac p12/dxale t3 p14/dxint p00 p01 p02 p03 p04 p05 p06 p07 v ss dp07/pwm07 dp06/pwm06 dp05/pwm05 dp04/pwm04 dp03/pwm03 dp02/pwm02 dp01/pwm01 dp00/pwm00 test/emu xtal1 xtal2 t1 dp12/afc2 dp11/afc1 dp10/afc0 dp21/scl dp20/sda c v dd int/t0 reset hsync vsync med171
1995 jun 15 7 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 5.2 pin description table 1 pin description for PCA84C646p and pca84c846p; sdip42 (see fig.2) symbol pin description vob 1 video fast blanking output signal. vow2 2 video character outputs or derivative port lines. dp22/vow1 3 dp23/vow0 4 vsync 5 vertical synchronization signal input, active low. hsync 6 horizontal synchronization signal input, active low. p10/ dxwr 7 port line 10 or emulation dxwr signal input. p11/ dxrd 8 port line 11 or emulation dxrd signal input. dp13/tdac 9 derivative i/o port or 14-bit d/a pwm. p12/dxale 10 port line 12 or emulation dxale signal input. t3 11 secondary 8-bit counter input pin (schmitt-trigger). p14/dxint 12 port line 14 or emulation dxint signal input. p00 to p07 13 to 20 general i/o port lines (10 ma). v ss 21 ground. dp00/pwm00 to dp07/pwm07 29, 28, 27, 26, 25, 24, 23, 22 derivative i/o port; 6-bit pwm (pwm04 to 07) or 7-bit pwm (pwm00 to 03). test/emu 30 control input of testing and emulation mode, normally low. xtal1 31 oscillator input terminal for system clock. xtal2 32 oscillator output terminal for system clock. reset 33 initialize input, active low. t1 34 direct testable pin and event counter input. int/t0 35 external interrupt/direct testable pin. dp12/afc2 36 derivative i/o port or comparator input with 4-bit dac. dp11/afc1 37 dp10/afc0 38 dp21/scl 39 derivative port line or i 2 c-bus clock line. dp20/sda 40 derivative port line or i 2 c-bus data line. c 41 external capacitor input for on chip pll osd oscillator. v dd 42 power supply.
1995 jun 15 8 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 6 reset the reset pin is used as an active low input to initialize the microcontroller to a defined state. a power-on-reset can be generated by using the rc-circuit as shown in fig.3. an active reset can be generated by driving the reset pin from an external logic device. such an active reset pulse should not fall off before v dd has reached its f xtal -dependent minimum operating voltage. 6.1 reset trip level the reset trip-voltage level is masked to 1.3 v in the PCA84C646 and pca84c846. 6.2 reset status derivative registers status; for details see table 40 program counter: 00h memory bank: 00h register bank: 00h stack pointer: 00h all interrupts disabled timer/event counter 1 stopped and cleared timer prescaler modulo-32 (ps = 0) timer flag cleared serial i/o interface disabled (eso = 0) and in slave receiver mode idle and stop mode cleared. fig.3 external components for reset pin. v (1) v PCA84C646/846 internal reset r c med172 dd ss reset reset reset ( 100 k w ) (1) to avoid overload of the internal diode, an external diode should be added in parallel if c reset > 0.2 m f. 7 analog control 7.1 6 and 7-bit pwm outputs (pwm00 to pwm07) the PCA84C646/pca84c846 has eight pwm outputs for analog controls of e.g. volume, balance, brightness and saturation. these pwm outputs generate pulse patterns with a repetition rate of 1 64 f pwm or 1 128 f pwm . the analog value is determined by the ratio of the high-time and the repetition time. a dc voltage proportional to the pwm control setting is obtained by means of an external integration network (low-pass filter). the eight pwm outputs are specified as follows: pwm00 to pwm03 outputs with 7-bit resolution pwm04 to pwm07 outputs with 6-bit resolution. figure 4 shows the block diagram of the 6-bit or 7-bit pwm dac. the polarity of the pwm0n output is selected as shown in table 2 by the polarity control bit p6lvl/p7lvl (derivative register 23; see table 25). the pwm0n output shares the pin with a dp0n i/o line under control of a pwmne enable bit; for selection see table 3. figure 5 shows the 6 and 7-bit pwm0n output patterns (non-inverted; p6lvl/p7lvl = 0). the high-time of a pwm0n output is t high = [ pwmndl ] t 0 where: [ pwmndl ] = the contents of pwmn data latch (n = 0 to 7; derivative register 10 to 17; see table 40) t 0 = 1/f pwm ; f pwm = 1 3 f xtal . table 2 polarity selection for the pwm0n output table 3 selection of pin function: dp0n/pwm0n (note 1) note 1. n = 0 to 7. p6lvl/p7lvl polarity 1 inverted 0 not inverted pwmne function 1 pwm0n output 0 dp0n i/o
1995 jun 15 9 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 handbook, full pagewidth med177 dp0n data i/o dp0n/pwm0n 6 or 7-bit pwm data latch p6lvl/p7lvl (1-bit) pwmne 6 or 7-bit dac pwm controller q q f xtal f pwm = 3 fig.4 block diagram of 6-bit or7-bit pwm dac. fig.5 example pwm0n output patterns (p6lvl/p7lvl = 0). handbook, full pagewidth f 64 or 128 1 2 3 m m + 1 m + 2 64 or 128 1 00 01 m 63 or 127 decimal value pwm data latch mlc261 xtal 3
1995 jun 15 10 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 7.2 vst control 14-bit pwm dac the PCA84C646 and pca84c846 have a pwm dac output (tdac) with a resolution of 16384 levels for voltage synthesized tuning (vst). figure 6 shows the block diagram of the 14-bit pwm dac which consists of: two 7-bit dac interface latches (see table 40): C vsth: derivative register 18; address 18h. C vstl: derivative register 19; address 19h. one 14-bit dac data latch: vstreg, which contents defines the high-time. 14-bit counter. pulse control. the contents of the interface latches vsth and vstl are latched into vstreg. the upper seven bits of vstreg are used for coarse adjustment, while the lower seven bits are used for fine adjustment. the contents of the interface latches vsth and vstl are latched into vstreg at the beginning of the first t sub after vstl is written (see fig.7). after vsth and vstl are latched into vstreg, it takes one t sub to generate the appropriate pulse pattern. therefore, to ensure correct digital-to-analog conversion, two t sub periods should be allowed before beginning the next sequence (changing the contents of vsth and vstl). to ensure that the correct data is latched into vstreg, vsth must contain the correct value before vstl is written; see the note in fig.7. the repetition times of the pulse controllers are: coarse, upper seven bits (vsth): fine, lower seven bits (vstl): output tdac shares the same pin as dp13; bit tdace (derivative register 22; see table 22) selects the function of pin dp13/tdac. table 4 selection of pin function dp13/tdac tdace function 1 tdac; 14-bit pwm output 0 dp13 t sub 128 3 f xtal = t r 128 t sub 49152 f xtal == 7.2.1 c oarse adjustment an active high pulse is generated in every subperiod; the pulse width being determined by the contents of vsth. the coarse output (out1) is low at the start of each subperiod and will remain low during where t s is the time within t subn . the output will then go high and remain high until the start of the next subperiod. the coarse pulse width may be calculated as: . 7.2.2 f ine adjustment fine adjustment is achieved by generating an additional pulse in specific subperiods. the pulse is added at the start of the selected subperiod and has a pulse width of 3/f xtal . the contents of vstl determine in which subperiods a fine pulse will be added. it is the logic 0 state of the value held in vstl that actually selects the subperiods. when more than one bit is a logic 0 then the subperiods selected will be a combination of those subperiods specified in table 5. for example, if vstl = 111 1010 then this is a combination of: vstl = 111 1110: subperiod 64 and vstl = 111 1011: subperiods 16, 48, 80 and 112. pulses will be added in subperiods 16, 48, 64, 80 and 112. this example is illustrated in fig.9. when vstl holds 111 1111 fine adjustment is inhibited and the tdac output is determined only by the contents of vsth. table 5 additional pulse distribution vstl additional pulse in subperiod 111 111 0 64 111 11 0 1 32 and 96 111 1 0 11 16, 48, 80 and 112 111 0 111 8, 24, 40, 56, 72, 88, 104 and 120 11 0 1111 4, 12, 20, 28, 36, 44, 52...116 and 124 1 0 1 1111 2, 6, 10, 14, 18, 22, 26, 30...122 and 126 0 11 1111 1, 3, 5, 7, 9, 11, 13, 15, 17...125 and 127 t s vsth 1 + () 3 f xtal ------------------------------------------- pulse duration 127 vsth C () 3 f xtal -------- =
1995 jun 15 11 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 fig.6 block diagram of the 14-bit pwm dac. dac interface 7-bit data latch (vsth) dac interface 7-bit data latch (vstl) 14-bit data latch (vstreg) ?ove instruction ?ov instruction data load timing pulse coarse 7-bit pwm fine additional pulse generator out2 out1 add q q p14lvl 14-bit counter q14 to 8 q7 to 1 pwm output polarity control bit tdac output f = f tdac xtal med179 7 msb lsb 7 7 7 load internal data bus 3 (1) (1) see fig.7 for timing.
1995 jun 15 12 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 fig.7 latching vsth, vstl into vstreg. t vsth vstl vsth vstl vsth,vstl is loaded into vstreg vsth,vstl is loaded into vstreg vstl case 3 case 2 case 1 vsth,vstl is loaded vsth into vstreg med180 sub t sub t sub t sub t sub t sub t sub t sub t sub in case 1 and case 2, a new value for vsth, vstl is latched into vstreg. in case 3, vstl, together with an old value of vsth are latched into vstreg. fig.8 tdac output (not inverted) with coarse adjustment only; vstl = 1111111; p14lvl = 0. handbook, full pagewidth 127 m m + 2 127 1 00 01 m 127 decimal value vsth data latch mgc573 f xtal 3 t subn 3/f xtal 01 (1) (1) (1) 2 m + 1 0 (1) t s vsth 1 + () 3 f xtal ------------------------------------------- =
1995 jun 15 13 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 fig.9 fine adjustment output (out2). handbook, full pagewidth mcd314 t sub0 t sub16 t sub32 t sub48 t sub64 t sub80 t sub96 t sub112 t sub127 t r 111 1110 111 1101 111 1011 111 1010 vstl vstl = 111 1010; additional pulses in subperiods 16, 48, 64, 80 and 112. fig.10 example of tdac (not inverted) output pulses for several values of vsth (t sub16 ). handbook, full pagewidth f 127 m t sub16 3/f xtal m + 2 127 1 00 01 m 127 decimal value vsth data latch mgc572 xtal 3 0 1 2 m + 1 0
1995 jun 15 14 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 8 afc input the afc input is intended to measure the level of the automatic frequency control (afc) signal. this is done by comparing the afc signal with the output of a 4-bit digital-to-analog converter as shown in fig.11. the dac analog switches select one of the 16 resistor taps that are connected between v dd and v ss (controlled by bits afcv3, afcv2, afcv1, afcv0; derivative register 20). the afcc signal (bit 0 in derivative register 20) then can be tested to check whether the afc input is higher or lower than the dac level. the afc inputs afc0, afc1 and afc2 share the same pins as derivative port lines dp10, dp11 and dp12. the pin functions are selected by bits afce0, afce1, afce2 (afc enable/disable bits; derivative register 22); for selection see table 6. afch1 and afch0 (derivative register 20) select one out of three afc inputs to the comparator; for a correct comparison, enable the corresponding afc input (afci) as shown in table 7. the conversion time of the afc is greater than 6 m s but less than 9 m s. it is recommended to add a nop instruction between the instruction which changes v ref or channel selection and the instruction which reads the afcc bit (compare bit). if the compare bit: afcc = 0, then the afc voltage < v ref . afcc = 1, then the afc voltage > v ref . table 6 selection of pin function dp1i/afci (i = 0, 1, 2) table 7 afc input selection bit value pin function comparator afce2 1 dp12 disabled 0 afc2 enabled afce1 1 dp11 disabled 0 afc1 enabled afce0 1 dp10 disabled 0 afc0 enabled afch1 afch0 select 0 0 afc channel 0; afc0 0 1 afc channel 1; afc1 1 0 afc channel 2; afc2 1 1 reserved fig.11 afc circuit. handbook, full pagewidth 4-bit d/a comparator afcv3 afcv2 afcv1 afcv0 afce0 afce1 afce2 afch1 afch0 med185 afc function enable selection afc value selection enable selector afc analog selector dp12/afc2 dp11/afc1 dp10/afc0 en (dp10 to dp12) en1 en2 en0 ?ov a, d20 instruction to read afccx bit internal bus channel selection
1995 jun 15 15 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 table 8 v ref as a function of afcv3 to afcv0 afcv3 afcv2 afcv1 afcv0 v ref v ref (v dd = 5.0 v) 0000 v dd 1 16 0.31 v 0001 v dd 2 16 0.62 v 0010 v dd 3 16 0.93 v 0011 v dd 4 16 1.25 v 0100 v dd 5 16 1.56 v 0101 v dd 6 16 1.87 v 0110 v dd 7 16 2.18 v 0111 v dd 8 16 2.50 v 1000 v dd 9 16 2.81 v 1001 v dd 10 16 3.12 v 1010 v dd 11 16 3.43 v 1011 v dd 12 16 3.75 v 1100 v dd 13 16 4.06 v 1101 v dd 14 16 4.37 v 1110 v dd 15 16 4.68 v 1111 v dd 5.00 v
1995 jun 15 16 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 9 osd (on screen display) function 9.1 features display ram: 64 10 bit. display character fonts: 64 (in which 62 customized + 2 special reserved codes). display starting position (of the first character): 64 different positions by software control, both vertical and horizontal. character size: 4 different character sizes, line-by-line basis, 1 dot = 1h/1v, 2h/2v, 3h/3v, 4h/4v. character matrix: 12 18 with no spacing between characters. foreground colours: 8, combination of red, green, blue; character-by-character basis. background/shadowing modes: 4, no background, box shadowing, north-west shadowing, frame shadowing (raster blanking), frame basis. background colours: 8, combination of red, green, blue; word-by-word basis. available when background mode is either in box shadowing or north-west shadowing and frame shadowing mode. on-chip osd oscillator. character blinking rate: 1 : 1, 1 : 3, 3 : 1 (frequency: 1 16 , 1 32 , 1 64 or 1 128 of f vsync , programmable, e.g. ntsc: 60 16 hz, pal: 50 64 hz etc.); character basis. display format: flexible display format by using carriage return (cr) code, maximum number of characters per line is flexible and depending on the osd clock. spacing between lines: 4 different choices from 0, 4, 8 or 12 horizontal scan lines. display character ram auto-address-post-increment when writing data. programmable hsync and vsync active input polarity. programmable g (vow1), b (vow2), r (vow0) and fb (vob) output polarity. 9.2 horizontal display position control the horizontal position counter is increased every osd clock (f osd ) cycle after the programmed level of hsync occurs at the hsync pin and is reset when the opposite polarity of the hsync is reached. horizontal start position is controlled by derivative register 36 (hpos; see table 36). the starting position is calculated as: hp = [4 (h5 to h0) + 5] (osd clock cycle) where (h5 to h0) = decimal value of register hpos; (h5 to h0) 3 10. 9.3 vertical display position control the vertical position counter is increased every hsync cycle and is reset by the vsync signal. vertical start position is controlled by derivative register 35 (vpos; see table 34). the vertical starting position is calculated as: vp = [4 (v5 to v0)] (horizontal scan lines) where (v5 to v0) = decimal value of register vpos; (v5 to v0) 3 0. 9.4 clock generator figure 12 illustrates the block diagram of the on-chip osd clock generator which consists of a phased-lock loop (pll) circuit. the voltage controlled oscillator (vco) outputs a clock (f vco ) with a frequency range of 8 to 20 mhz (see fig.12). the input signal f 1 = hsync. the programmable active level detector: passes signal f 1 , when hsync is active high, or inverts signal f 1 , when hsync is active low. the output signal f 2 is always active high. the vco is synchronized with the high-to-low edge of the f 2 signal. the value programmed in the 7-bit pll programmable counter control register (pllcn; derivative register 25; see table 40) determines: f vco =f 1 16 (decimal value of 7-bit counter); where 16 < (decimal value of 7-bit counter) < 48. the value 16 is the 4-bit prescaler which increases or decreases the output of the vco in steps of (16 f 1 ). given an example of f 1 = 15.750 khz, the f vco is then increased or decreased in steps of 16 15.750 khz = 252 khz = 0.25 mhz. the f vco is fed into a buffer to generate the osd dot clock frequency signal (f osd ); 4 mhz f osd 12 mhz. decreasing f osd gives broader characters. recommended: 4 mhz f osd typical 12 mhz. the osd clock is enabled/disabled by the state of the en bit (derivative register 34; see also section 12.4). when the osd clock is disabled (f osd = low) the oscillator remains active, therefore the transient time from the osd clock start-up to locking into the external hsync signal is reduced. as the on-chip oscillator is always active after power-on, when the osd clock is enabled no large currents flow (as for rc or lc oscillators) and therefore radiated noise is dramatically reduced.
1995 jun 15 17 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 9.4.1 m ounting precautions to achieve good osd performance, take the following precautions for the microcontroller mounting: apply the recommended r, c s and c p (pll loop filter) values as shown in fig.12 and place them as close as possible to pin c (41). to guarantee stable pll operation, apply a noise-free hsync signal (pin 6). avoid heavy loading of the output pins. the supply voltage (v dd ) must be correctly decoupled. connect decoupling capacitors as close as possible to the v dd and v ss pins. position microcontroller optimal and away from components bearing high voltage and/or strong current. pll loop filter ground of capacitors c s and c p must be directly connected to the v ss pin (21). avoid a ground loop and separate the ground from other digital signals ground. the connection between v ss pin (21) and +5 v regulator ground/switching power supply secondary ground must be as short as possible. fig.12 on-chip osd oscillator. handbook, full pagewidth med196 voltage controlled oscillator charge pump and loop filter phase/ frequency detector active level detector programmable 7-bit counter f osd (osd clock) divided by n standby f 2 f 1 hsync 16 osd disable c c s f vco c p r (2) (1) (1) r=10to47k w ; typ. 15 k w . c s = 100 to 470 nf; typ. 220 nf. c p = 1 10 c s . for mounting see section 9.4.1 mounting precautions. (2) example: if f 1 = 15.750 khz and (decimal value of 7-bit counter) = 32 then f vco = 8.064 mhz and the output of the programmable 7-bit counter is 15.750 khz.
1995 jun 15 18 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 handbook, full pagewidth med189 c on-chip oscillator hsync vsync internal synchronous circuit instruction decoder control register control signals horizontal position register/ counter character size control vertical position register/ counter counter write address address buffer selector display character ram display bit pattern display control and output stage control register rgbfb vow1 vow0 vow2 vob cpu bus rom(64) fig.13 osd block diagram.
1995 jun 15 19 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 10 display ram organization the display ram is organized as 64 10 bits. the general format of each ram location is as follows: bits <9-4> hold data, comprising: C customer designed character font codes (62) C carriage return code (1) C space code (1). bits <3-0> contain the attributes of the character font: C foreground colour and blinking C character size and line space C background colour and end-of-display . 10.1 description of display ram codes there are three data formats for the display ram code 1. character font code 2. carriage return code 3. space code. the three data formats and their descriptions are shown in tables 9 to 17. figure 14 illustrates an example of the timing of fb, r, g, and b pulses when displaying a line of dots stream in a character. fb = vob; r = vow0, g = vow1; b = vow2. figure 15 shows an example of the screen which includes some cariage return and space codes. table 9 format of character font code table 10 description of character font code bits table 11 selection of background and foreground colour 987654321 0 c5 c4 c3 c2 c1 c0 t3 t2 t1 t0 character font code (00h - 3dh) foreground colour blink symbol description c5 to c0 if bits <9-4> are in the range (00h to 3dh), then this is a character font code and 1 from 62 customer designed character fonts can be selected. t3 to t1 bits <3-1> determine the (foreground) colour (1 out of 8) of this character; see table 11. t0 blinking of this character is controlled by bit <0>. see section 12.3 for duty cycle and frequency control. when t0 = 0; blinking is off. when t0 = 1; blinking is on. blinking rate: 1 16 , 1 32 ,1 64 or 1 128 f vsync . t3 (red) t2 (green) t1 (blue) colour 0 0 0 black 0 0 1 blue 0 1 0 green 0 1 1 cyan 100red 1 0 1 magenta 1 1 0 yellow 1 1 1 white
1995 jun 15 20 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 table 12 format of carriage return code table 13 description of carriage return code bits; format is shown in table 12 9876543210 c5 c4 c3 c2 c1 c0 t3 t2 t1 t0 carriage return code (3eh) character size line spacing symbol description c5 to c0 if bits <9-4> hold 3eh, then this is the carriage return code. the current display line is terminated (a transparent pattern appears on the screen) and the next character will be displayed at the beginning of the next line. t3 to t2 bits <3-2> select the size of the of the character to be displayed on the next line; see table 14. t1 to t0 bits <1-0> determine the spacing between lines of displayed characters. spacing is a multiple of the number of horizontal scan lines. in order to prevent vertical jumping of the display, the first line should be a non-displayed line i.e. the carriage return code. the line spacing for this code must not be zero; see table 15. table 14 selection of character size note 1. h is the osd clock period; v is the number of horizontal scan lines per dot. t3 t2 character dot size (1) 0 0 1h/1v 0 1 2h/2v 1 0 3h/3v 1 1 4h/4v table 15 selection of line spacing t1 t0 line spacing 0 0 0h line 0 1 4h line 1 0 8h line 1 1 12h line table 16 format of space code table 17 description of space code bits; format is shown in table 16 987654321 0 c5 c4 c3 c2 c1 c0 t3 t2 t1 t0 space code (3fh) background colour end symbol description c5 to c0 if bits <9-4> hold 3fh, then this is the space code. a transparent pattern, equal to one character width, will be displayed on the screen. t3 to t1 bits <3-1> determine the background colour of the characters including the space code in box shadowing mode but following the space code in north-west shadowing mode. see section 12.4 for more details. background colour selection is the same as foreground colour selection; see table 11. t0 bit <0> is the end-of-display bit and indicates the end of display of the current screen before exhaustion of display ram. the last character displayed on the tv screen is either the 64 th ram location or a space code with the end-of-display attribute set to logic 1. when t0 = 0; continue display of next character. when t0 = 1; end of display.
1995 jun 15 21 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 fig.14 r, g, b and fb timing. handbook, full pagewidth r g b i fb sp code sp code acm "s" : red colour "e" : b+i colour "i" : green colour 1st sp code : acm = on "z" : g+b+i colour 2nd sp code : acm = off med204 handbook, full pagewidth vstart hstart volume channel cr t h e n e w f u n c i o n t i n p c f 8 5 c x x sp sp cr cr cr e l c o m e w cr cr st a ndal x hi ! thi s i s sp sp cr line spacing 1 = 4h line spacing 2 = 8h line spacing 3 = 0h line spacing 4 = 0h line spacing 6 = 0h sp four different background colours (in box shadowing mode): black red green blue line spacing 4 = 4h med205 fig.15 on-screen-display (an example).
1995 jun 15 22 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 10.2 loading character data into display ram three derivative registers are used to address and load data into the display ram. these registers (configurations are shown in tables 18, 19 and 20) are described in the following sections. 10.2.1 dcr a ddress r egister (dcrar) table 18 dcrar (address 30h) this is derivative register 30 and bits <5-0> holds the address of the location in display ram to which the data held in registers dcrtr and dcrcr will be written to. bits <7-6> are reserved. 10.2.2 dcr a ttribute r egister (dcrtr) table 19 dcrtr (address 31h) this is derivative register 31 and holds the character font attribute data. the data will be loaded into bits <3-0> of the location in ram pointed to by the contents of dcrar. bits <7-4> are reserved. 10.2.3 dcr c haracter r egister (dcrcr) table 20 dcrcr (address 32h) this is derivative register 32 and holds the character data that will be loaded into bits <9-4> of the location in ram addressed by the contents of dcrar. bits <7-6> are reserved. 10.3 writing character data to display ram 1. select the start address in display ram. the start address is stored in dcrar and can take any value between 0 and 63. 76543210 -- a5 a4 a3 a2 a1 a0 76543210 ---- t3 t2 t1 t0 76543210 -- c5 c4 c3 c2 c1 c0 2. load the character attributes into dcrtr. if the attributes of a series of displayed characters are the same, only dcrcr needs to be updated. the meaning of the attributes (4 bits) is dependent on the contents of the next command (the data in the dcrcr bits <5-0>; i.e. carriage return code, space code or character font code). 3. load the character data into dcrcr. this operation loads the selected ram location with the data held in registers dcrtr and dcrcr. the address held in dcrar is then incremented by 1 pointing to the next ram location in anticipation of the next operation. overflow of the dcrar, i.e. overflow from 63 to 64, makes it reset to zero. after the instruction mov d32h, a is finished, the post-increment operation is performed automatically. auto-post-increment operation: begin (dcrar) (dcrar) + 1 if (dcrar) > 63 then (dcrar) 0 end after master reset the initial values of dcrar, dcrtr and dcrcr are all zero. figure 16 shows how dcrar is incremented and advanced. 10.4 default value of the display character the default values of the display characters, after master reset, are as follows: background colour = blue (r = 0, g = 0, b = 1) character size = 1v/1h end-of-display control bit = 0. if another set-up is needed, the first character should be sp code and second character is cr code to define the character size and background colour. handbook, halfpage 17 00 01 02 03 04 61 62 63 18 19 dcrar med208 fig.16 dcrar increment cycle.
1995 jun 15 23 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 11 character rom each character font is stored in the on-chip character rom in a 12 19 dot matrix. however, only elements in rows 1 to 18 (12 18 dot matrix) can be selected as visible dots on the screen. row 0 is only used for the combination of two characters in a vertical direction when north-west shadowing mode is selected (for details see section 12.4). row 0 contains the same bit pattern of row 18 of the character above it. if no combined character in vertical direction is intended for this character, row 0 should be filled with all zeros. 11.1 character rom organization rom is divided into two parts: rom1 and rom2. the organization of the bit patterns stored in rom1 and rom2 and the file format to submit to philips for customized character sets is shown in fig.17. a software package (osdgem) that assists in the design of character fonts on-screen and that also automatically generates the bit pattern hex files is available on request. the package is run under the ms-dos environment for ibm compatible pcs. regarding fig.17 the following points should be noted. 1. row 0 of each font is reserved for vertical combination of two fonts. 2. binary 1 denotes visual dots. 3. rom1 and rom2 data files are in intel hex format on a byte basis. each byte is structured high nibble followed by low nibble. 4. the unused last byte of each font in rom1 must be filled with ffh. 5. the unused last 2 1 2 bytes in rom2 must be filled with the same data as held in the corresponding address in rom1. 6. the data bytes of the last 2 reserved fonts (carriage return and space codes) should be filled with 00h. 7. cs denotes checksum. handbook, full pagewidth 11 10 9 8 7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 column row lsb msb rom1 rom2 rom1 rom2 rom1 rom2 rom1 rom2 rom1 rom2 rom1 rom2 rom1 rom2 rom1 rom2 rom1 rom2 rom1 0 0 0 2 2 0 3 f c 2 2 0 2 2 0 3 f f 0 0 1 5 5 2 0 0 c 0 3 0 0 0 0 2 2 0 3 f c 2 2 0 2 2 0 3 f f 0 0 1 5 5 2 0 0 c 0 3 0 rom1 rom2 3 f c 2 2 0 2 2 0 3 f c 2 2 0 0 0 1 5 5 3 0 0 6 0 5 8 3 f c 2 2 0 3 f c 2 2 0 0 0 1 5 5 3 0 0 6 0 5 8 rom1 : 1 0 0 0 0 0 0 0 00 00 22 fc 03 22 20 f2 3f 01 20 55 0c 00 03 : 1 0 0 0 1 0 0 0 < - - - data for font 2 - - - 12 34> : 1 0 0 0 2 0 0 0 < - - - data for font 3 - - - 56 78> byte # __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ 0 1 2 3 4 5 6 7 8 9 a b c d e f f f f f f f rom2 : 1 0 0 0 0 0 0 0 fc 03 22 20 c2 3f 20 12 00 53 65 00 58 : 1 0 0 0 1 0 0 0 < - - - data for font 2 - - - > : 1 0 0 0 2 0 0 0 < - - - data for font 3 - - - > 5 x 78 ff 0 0 03 ff 1 x 34 ff > > > 2 2 0 cs cs cs cs cs cs mlb760 fig.17 font pattern stored in character rom1 and rom2.
1995 jun 15 24 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 12 osd control registers the functions of the osd circuitry are controlled by the derivative registers as shown in table 21. table 21 osd control registers overview name derivative register function number addr con1 22 22h enable tdac; the i 2 c-bus lines; the afc functions and the vow0 and vow1 lines. con2 23 23h selects the output polarity of the pwm outputs and also enables and selects the vsync interrupt. con3 33 33h selects the blinking frequency and the active ratio of the blinking frequency for the osd. con4 34 34h selects the 4 display modes; the active state of hsync and vsync and the output polarity of the fb and vow0 to vow2 outputs. it also enables/disables the osd clock. vpos 35 35h selects the vertical starting position of the display row. hpos 36 36h selects the horizontal starting position of the display row. bcc 37 37h selects the background colour.
1995 jun 15 25 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 12.1 derivative register 22 (con1) table 22 derivative register 22 (address 22h) table 23 description of derivative register 22 bits 76543210 tdace scle sdae adc2e adc1e adc0e vow1e vow0e bit symbol description 7 tdace pulse width modulated output tdac enable bit. when: tdace = 1; pin dp13/tdac is selected as output tdac. tdace = 0; pin dp13/tdac is selected as derivative port line dp1. 6 scle i 2 c-bus clock enable bit. when: scle = 1; pin dp21/scl is selected as scl (i 2 c-bus clock line). scle = 0; pin dp21/scl is selected as derivative port line dp21. 5 sdae i 2 c-bus data enable bit. when: sdae = 1; pin dp20/sda is selected as sda (i 2 c-bus data line). sdae = 0; pin dp20/sda is selected as derivative port line dp20. 4 afce2 these 3 bits select the pin function of dp1i/afc and enable/disable the comparator in the afc circuit; for the selection and enable/disable function see table 7. 3 afce1 2 afce0 1 vow1e pin function selection bit. when: vow1e = 1; pin dp22/vow1 is selected as vow1. vow1e = 0; pin dp22/vow1 is selected as derivative port line dp22. 0 vow0e pin function selection bit. when: vow0e = 1; pin dp23/vow1 is selected as vow1. vow0e = 0; pin dp23/vow1 is selected as derivative port line dp23.
1995 jun 15 26 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 12.2 derivative register 23 (con2) table 24 derivative register 23 table 25 description of derivative register 23 bits 76543210 vint vien --- p14lvl p7lvl p6lvl bit symbol description 7 vint bit vint indicates if the interrupt comes from vsync (if vint = 1 and vien = 1) or i 2 c-bus when the cpu gets interrupted by interrupt vector address 7. 6 vien the vsync leading edge (active level detection automatically done by the PCA84C646/pca84c846) generates an interrupt if bit vien = 1 and the sio interrupt is enabled (i.e. the i 2 c-bus and the vsync interrupt shares the same interrupt vector). 5to4 - these three bits are reserved. 2 p14lvl polarity select bit for output tda. when: p14lvl = 1; the tdac output is inverted. p14lvl = 0; the tdac output is not inverted. 1 p7lvl polarity select bit for outputs pwm00 to pwm03. when: p7lvl = 1; the outputs pwm00 to pwm03 are inverted. p7lvl = 0; the outputs pwm00 to pwm03 are not inverted. 0 p6lvl polarity select bit for outputs pwm04 to pwm07. when: p6lvl = 1; the outputs pwm04 to pwm07 are inverted. p6lvl = 0; the outputs pwm04 to pwm07 are not inverted.
1995 jun 15 27 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 12.3 derivative register 33 (con3) derivative register 33 is to control the character blinking related operation. figure 18 shows the timing diagram of character blinking frequency and blinking ratio. table 26 derivative register 33 table 27 description of derivative register 33 bits 76543210 ---- br1 br0 bf1 bf0 bit symbol description 7 to 4 - these 4 bits are reserved. 3 br1 blinking active ratio select bits. these two bits allow one from a choice of three active blinking ratios to be selected; see table 28. 2 br0 1 bf1 blinking frequency select bits. these two bits allow one from a choice of four blinking frequencies to be selected. , where 2 (bf1, bf0) is a decimal value determined by bits bf1 and bf0; see table 29. 0 bf0 blinking frequency f vsync 16 2 bf1, bf0 () ---------------------------------------- hz = table 28 active ratio determined by bits br1 and br0 br1 br0 active ratio 0 0 3 : 1 (default) 0 1 1:1 1 0 1:3 1 1 reserved table 29 blinking frequency determined by (bf1,bf0) bf1 bf0 2 (bf1, bf0) blinking frequency (hz) 00 1 1 16 f vsync 01 2 1 32 f vsync 10 4 1 64 f vsync 11 8 1 128 f vsync (default) handbook, full pagewidth vsync vsync 01 23 78 1011 60 hz 14 15 01 23 78 1011 60 hz 14 15 blinking frequency: blinking ratio: 1 : 3 blinking frequency: blinking ratio: 1 : 1 blinking frequency: blinking ratio: 3 : 1 blinking frequency: blinking ratio: 1 : 3 blinking frequency: blinking ratio: 1 : 1 blinking frequency: blinking ratio: 3 : 1 mra848 f 16 vsync f 16 vsync f 16 vsync f 32 vsync f 32 vsync f 32 fig.18 example of character blinking (ntsc 525lpf/60hz).
1995 jun 15 28 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 12.4 derivative register 34 (con4) this register selects the 4 display modes(mode 0 to mode 3); the active state of hsync and vsync and the output polarity of the fb and vow0 to vow2 outputs. it also enables/disables the osd clock (f osd ). table 30 derivative register 34 table 31 description of derivative register 34 bits table 32 selection of display modes 76543210 -- s1 s0 hp vp bp en bit symbol description 7 - these two bits are reserved. 6 - 5 s1 display mode select bits; see table 32. 4s0 3hp hsync signal polarity control bit (see fig.19). when hp = 1; the active level of hsync is high. when hp = 0; the active level of hsync is low (default state). 2vp vsync signal polarity control bit (see fig.19). when vp = 1; the active level of vsync is high. when vp = 0; the active level of vsync is low (default state). 1 bp output polarity control bit for fb, vow0, vow1 and vow2 (see fig.20). when bp = 1; the polarity of fb, vow0, vow1 and vow2 is high (default state). when bp = 0; the polarity of fb, vow0, vow1 and vow2 is low. 0 en osd clock enable/disable bit. when en = 1; the osd clock is enabled. when en = 0; the osd clock is disabled. s1 s0 display mode 0 0 mode 0 no background mode (see fig.21). the osd fonts/characters are directly superimposed on the tv video signals. 0 1 mode 1 north-west shadowing mode (see fig.22). available only in the character size 2v/2h or 4v/4h (v: horizontal line; h: osd clock).the shadows of the characters are generated by placing a light source on the north-west 45 degree direction (see also figs 25 and 26). when designing the character bit pattern, care must be taken that the shadows generated by this mode is only within the cell boundary in vertical direction (see figs 28 and 29 for details). but shadows generated by this mode in horizontal direction has no boundary limitation (fig.30). 1 0 mode 2 box shadowing mode (see fig.23). box shadowing is to surround the character font by a 12 18 dots box in background, i.e. within the character font cell; locations with no foreground dots are filled with background dots (see fig.27). 1 1 mode 3 frame shadowing mode (raster blanking; see fig.24); background colour displayed on full screen where no bit patterns are on.the background colour is controlled by derivative register 37 and has 8 different colours; see table 39.
1995 jun 15 29 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 fig.19 bits hp/vp determine the active level of the hsync/ vsync signal. handbook, full pagewidth hsync/vsync pin hsync/vsync pin hp/vp = 1 (active high) hp/vp = 0 (active low) character display interval character display interval med195 fig.20 bit bp determines the active level of fb, r, g and b. handbook, full pagewidth fb (r, g, b ) fb ( r, g, b ) bp = 1 (active high) bp = 0 (active low) character display interval character display interval med194
1995 jun 15 30 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 fig.21 mode 0: no background (superimpose) mode. m o s "m" -- (r+b) "o" -- (b) "s" -- (r+g) fb sp code sp code r g b i suppose the colour of each character is as follows: med211
1995 jun 15 31 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 fig.22 mode 1: north-west shadowing mode. available only in character size 2v/2h or 4v/4h. handbook, full pagewidth : background colour fb r g b 1dosc assume : 1. 1st char in (g+b) colour 2. 2nd char in (g+b) 3. background colour : r+b med212
1995 jun 15 32 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 fig.23 mode 2: box shadowing mode. handbook, full pagewidth background colour column 0 column 11 row 0 row 17 med213
1995 jun 15 33 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 fig.24 mode 3: frame shadowing mode. handbook, full pagewidth background colour = blue med214
1995 jun 15 34 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 handbook, full pagewidth 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 01234567891011 1v 1h med215 fig.25 example of north-west shadowing mode; size = 2v/2h.
1995 jun 15 35 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 fig.26 example of north-west shadowing mode; size = 4v/4h. handbook, full pagewidth 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 01234567891011 2v 2h med216
1995 jun 15 36 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 01234567891011 size = 1 size = 2 size = 3 size = 4 med217 fig.27 example of box shadowing mode.
1995 jun 15 37 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 handbook, full pagewidth 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 character designed in character rom character displayed on tv screen med218 fig.28 example 1: north-west shadowing mode; shadow within cell boundary.
1995 jun 15 38 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 handbook, full pagewidth 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 character designed in character rom character displayed on tv screen med219 fig.29 example 2: north-west shadowing mode; shadow out of cell boundary.
1995 jun 15 39 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 fig.30 north-west shadowing. 0123 45678 91011 012 34567 891011 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 two characters designed in character rom separately two characters displayed on tv screen 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 012 345678 91011012 345678 91011 cell boundary med220 (2) (2) (1) (1) horizontal shadowing overflow into the next character cell. (2) vertical shadowing overflow does not show beyond the bottom of a cell.
1995 jun 15 40 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 12.4.1 s pace c ode and c arriage r eturn c ode in different background / shadowing modes mode 0 no background mode. both the space code and the carriage return code are displayed as transparent (no bit) patterns, with the video signal as the background. mode 1 north-west shadowing mode. similar to mode 0. mode 2 box shadowing mode. the space code is displayed as a transparent pattern with selected background colour. this will also be the background colour of the character following the space code. however, when the space code is used as an end bit, it will be displayed as a transparent pattern superimposed on the video. the carriage return code in mode 2 is also displayed as a transparent pattern superimposed on the video signal. mode 3 frame shadowing mode. the space code and carriage return code is displayed as a transparent pattern with background colour; see table 39. space code and carriage return code in the 4 different background/shadowing modes (0 to 3), with: blinking off are shown in figs 31, 32, 33 and 34. blinking on are shown in figs 36, 37, 38 and 39. figure 39 shows blinking of a character only within the 12 18 cell boundary. if the shadow of the blinking character crosses over the boundary of the cell of the character next to the one that is not blinking, the shadow dot will still appear on the screen regardless whether the blinking character is on or off. fig.31 sp and cr codes in mode 0: no background mode (superimpose; transparent pattern). handbook, full pagewidth 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 012345 67 891011 012345 67 891011 sp code cr code 012345 67 891011 012345 67 891011 red colour blue colour med227
1995 jun 15 41 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 fig.32 sp and cr codes in mode 1: north-west shadowing mode (transparent pattern). handbook, full pagewidth 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 012345 67 891011 012345 67 891011 sp code cr code 012345 67 891011 012345 67 891011 red colour blue colour (background) black colour (background) green colour med228
1995 jun 15 42 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 fig.33 sp and cr codes in mode 2: box shadowing mode. handbook, full pagewidth red colour blue colour cr code 012345 67 891011 012345 67 891011 (background) yellow colour (background) cyan colour 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 012345 67 891011 012345 67 891011 sp code med229 sp code is a transparent pattern with the background colour of the character it intends to change or keep. cr code is always a transparent pattern with the video signal as its background. sp code can change the background colour of itself and the character/word next to it (in this example: from cyan to yellow).
1995 jun 15 43 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 fig.34 sp and cr codes in mode 3: frame shadowing mode. sp and cr codes are all transparent pattern with the background colour as its colour. handbook, full pagewidth red colour blue colour cr code 012345 67 891011 012345 67 891011 (background) yellow colour 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 012345 67 891011 012345 67 891011 sp code med230
1995 jun 15 44 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 a ge = 296 mm (datasheet) 27 mm red colour blue colour sp code cr code sp code cr code sp code cr code character on character off character on med231 fig.35 sp and cr codes in mode 0: no background mode (superimpose; transparent pattern) with blinking of character is set to active.
1995 jun 15 45 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 / 1 page = 296 mm (datasheet) 27 mm sp code cr code sp code cr code sp code cr code red colour blue colour (background) black colour (background) green colour character on character off character on med232 fig.36 sp and cr codes in mode 1: north-west shadowing mode (transparent pattern) with blinking of character is set to active.
1995 jun 15 46 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 e = 296 mm (datasheet) 27 mm cr code sp code cr code sp code cr code sp code red colour blue colour (background) yellow colour (background) cyan colour character on character off character on med234 fig.37 sp and cr codes in mode 2: box shadowing mode with blinking of character set to active.
1995 jun 15 47 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 1/1 page = 296 mm (datasheet) 27 mm cr code sp code cr code sp code cr code sp code red colour blue colour (background) yellow colour character on character off character on med235 fig.38 sp and cr codes in mode 3: frame shadowing mode with blinking of character set to active.
1995 jun 15 48 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 handbook, full pagewidth 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 01234 567 8 9101101234 567891011 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 0123456789101101234567891011 in this example: - 1st character is in blinking mode - 2nd character is not - the first character bit pattern is designed such that the north-west shadow of the 1st character falls into the cell of 2nd character. when the 1st character is blinking and displayed on the screen there is no problem. however, when the 1st character is off then the shadow of the 1st character falls into 2nd character cell and will remain there. to avoid this happening: - design bit pattern in such a way that shadow does not cross the cell boundary - make adjacent characters all blinking or all not blinking. med236 - 1 fig.39 blinking of character is within the character cell only (12 18).
1995 jun 15 49 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 12.5 derivative register 35 (vpos) derivative register 35 selects the vertical starting position of the display row. table 33 derivative register 35 (address 35h) table 34 description of derivative register 35 bits 12.6 derivative register 36 (hpos) derivative register 36 selects the horizontal starting position of the display row. table 35 derivative register 36 (address 36h) table 36 description of derivative register 36 bits 76543210 -- v5 v4 v3 v2 v1 v0 bit symbol description 7 to 6 - reserved. 5 v5 these 6 bits enable 1 of 64 vertical start positions to be selected for the display row. the vertical starting position is calculated as follows: where (v5 to v0) is the decimal value of the contents of register 35; (v5 to v0) 3 0. 4v4 3v3 2v2 1v1 0v0 76543210 -- h5 h4 h3 h2 h1 h0 bit symbol description 7 to 6 - reserved. 5 h5 these 6 bits enable 1 of 64 horizontal start positions to be selected for the display row. the horizontal starting position is calculated as follows: where (h5 to h0) is the decimal value of the contents of register 36; (h5 to h0) 3 10. 4h4 3h3 2h2 1h1 0h0 vp 4 v5 to v0 () [] horizontal scan lines = hp 4 h5 to h0 () 5 + [] osd clock cycle =
1995 jun 15 50 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 12.7 derivative register 37 (bcc) derivative register 37 selects the background colour when the osd is in frame shadowing mode. table 37 derivative register 37 table 38 description of derivative register 37 bits table 39 selection of background colour in frame shadowing mode 76543210 ----- bcr bcg bcb bit symbol description 7to3 - reserved. 2 bcr these three bits are used to select the background colour in frame shadowing mode; see table 39. 1 bcg 0 bcb bcr (red) bcg (green) bcb (blue) colour 0 0 0 black 0 0 1 blue 0 1 0 green 0 1 1 cyan 100red 1 0 1 magenta 1 1 0 yellow 1 1 1 white
1995 jun 15 51 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 13 combination of two or more font cells to form a new font the user can combine two (or more) font cells to form a new higher resolution pattern; see figs 40, 41, 42 and 43. combination of two cells in horizontal direction needs no special care. all 4 background/shadowing modes are applicable; see figs 40 and 41. however the combination of two cells in a vertical direction needs the following special care: space between two rows should be programmed as 0 (bit < 1-0 > of carriage return code = 00). row 0 in the character rom is to be used in the north-west shadowing mode. if this mode is intended for use by this formed character font, the row 0 should contain the bit pattern of row 18 of the font above it (see figs 42 and 43). fig.40 combination of two character cells in horizontal direction to form a new font; without shadowing. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 01234567891011 01234567891011 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 mra849
1995 jun 15 52 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 fig.41 combination of two character cells in horizontal direction to form a new font; with north-west shadowing. handbook, full pagewidth 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 01234567891011 01234567891011 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 mra850
1995 jun 15 53 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 fig.42 combination of two characters in vertical direction to form a new pattern; contents row 18 (upper cell) not equal to contents of row 1(lower cell). 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 01234567891011 01234567891011 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 cell boundary 01234567891011 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 01234567891011 18 med224 character pattern displayed on the screen character pattern stored in the rom/ram (2) (1) (1) the bit pattern of row 18 of the upper character is not equal to that of row 0 of the lower character. (2) due to the situation of (1), in the north-west shadowing mode a gap in the shadow might occur.
1995 jun 15 54 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 fig.43 combination of two characters in vertical direction to formulate a new pattern; contents row 18 (upper cell) equal to contents of row 1(lower cell). 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 01234567891011 01234567891011 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 cell boundary 01234567891011 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 01234567891011 18 med225 character pattern displayed on the screen character pattern stored in the rom/ram (2) (1) (1) the bit pattern of row 18 of the upper character is equal to that of row 0 of the lower character. (2) due to the situation of (1), in the north-west shadowing mode a gap in the shadow is avoided.
1995 jun 15 55 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 14 osd clock in different tv standards 14.1 maximum number of characters per row the number of characters per row is a function of the osd clock frequency and the tv standard used. the active video signal period of a horizontal line is 53.5 m s (see fig.44). however, in order to reduce the jittering of the screen edge, overscan is normally applied by the tv manufacturer and this reduces the visible video signal period to 9 10 53.5 m s = 48.15 m s. the examples given below show how the number of characters per row and the character width may be obtained for the ntsc 525lpf/60 hz tv standard using different osd clock frequencies. 14.1.1 e xample 1 for the osd clock frequency f osd = 6 mhz; clock period = 0.166 m s. the number of visible dots on one horizontal line is 290 (48.15 m s/0.166 m s). start of the first character dot is roughly 45 dots after hsync (see section 9.2; command b, c, d). therefore 290 - 45 = 245 dots are visible. since each character is composed of 12 18 dots, the maximum characters displayed on a row is 20 (245/12). on a 19" tv screen, the width of a horizontal line is approximately 370 mm and this gives a character width of 18.5 mm (370 mm/20). 14.1.2 e xample 2 for the osd clock frequency f osd = 10 mhz; clock period = 0.1 m s. the number of visible dots on one horizontal line is 481 (48.15 m s/0.1 m s). start of the first character dot is roughly 45 dots after hsync (see section 9.2; command b, c, d). therefore 481 - 45 = 436 dots are visible. since each character is composed of 12 18 dots, the maximum characters displayed on a row is 36 (436/12). on a 19" tv screen, the width of a horizontal line is approximately 370 mm and this gives a character width of 10.3 mm (370 mm/36). 14.2 maximum number of rows per frame the number of rows per frame is a function of the number of active lines per display field and the number of vertical dots in the character matrix (which is 18). the number of rows per frame (n) is calculated as shown below. the three examples shown below illustrate how the maximum number of rows per frame is obtained for each tv scanning standard. 14.2.1 e xample 1; ntsc 525lpf/60 h z the number of active lines per field for this standard is between 241.5 and 249.5h (see fig.45). if the value of 241 is used then the maximum number of rows per frame is 13. 14.2.2 e xample 2; pal 625lpf/50 h z with this standard it is not necessary to divide hsync by two as both the horizontal and vertical frequency are doubled. the maximum number of rows per frame is 15. n number of active lines per field 18 -------------------------------------------------------------------------------- - =
1995 jun 15 56 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 handbook, full pagewidth mra862 blacker than black, 100% blanking level 75% black, 67.5 2.5% composite video signal 0 white, 12.5 2.5% right left 0 horizontal deflection sawtooth trace retrace begins retrace retrace ends blanking begins blanking ends fig.44 composite video signal for three horizontal lines compared to three horizontal deflection sawteeth (ntsc 525lpf/60 hz).
1995 jun 15 57 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 handbook, full pagewidth mra863 equalizing pulse interval vertical sync pulse interval equalizing pulse interval blacker than black black level white level zero carrier horizontal blanking picture bottom of picture vertical blanking 0.05 v 0.03 v 0 3h 3h 3h h hh 0.5 h h 0.5 h h 100% (75 2.5)% (12.5 2.5)% 0% start of next field first field, 262.5 h 16.666 s or 1/60 s second field, 262.5 h 16.666 s or 1/60 s vertical blanking period 13 to 21 h active lines 241.5 to 249.5 h vertical blanking period 13 to 21 h (825.5 to 1335.5 s) active lines 241.5 to 249.5 h right left horizontal deflection sawtooth trace trace vertical deflection sawtooth bottom top first field vertical deflection sawtooth blanking begins blanking ends retrace 500 to 750 s second field vertical deflection sawtooth retrace m m m m fig.45 vertical sync and blanking pulse intervals for one frame (ntsc 525lpf/60 hz).
1995 jun 15 58 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 15 t3: 8-bit counter figure 46 shows the block diagram of the 8-bit counter. a schmitt-trigger input pin shapes the slow slope of the input signal into a square wave. the rising edge of the signal increases the (ripple) counter by 1. the data in the counter can be read by instruction mov a, d24h (derivative register 24). as soon as data is read, this counter is reset to zero . overflow or power-on-reset both reset the counter value to zero . minimum distance between two successive pulses (rising edges) is 30 m s. 16 i 2 c-bus master slave transceiver the i 2 c-bus master and slave transceiver is integrated. in control register con1 (derivative register 22) bits scle and sdae select the function of pins dp20/sda and dp21/scl (for selection see table 23); sda = i 2 c-bus data and scl = clock line. both pins are only available in port option 2 (see fig.48). fig.46 t3: 8-bit counter block diagram. h andbook, full pagewidth mlc075 t3 power-on-reset read d24 8-bit counter read enable reset q0 to q7 ck data bus
1995 jun 15 59 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 17 derivative registers table 40 register map PCA84C646/pca84c846 values within parenthesis show the bit state after a reset operation; x denotes an undefined state. addr (hex) reg76543210r/w 00 dp0r (terminal) dp07 (x) dp06 (x) dp05 (x) dp04 (x) dp03 (x) dp02 (x) dp01 (x) dp00 (x) r 01 dp1r (terminal) - (x) - (x) - (x) - (x) dp13 (x) dp12 (x) dp11 (x) dp10 (x) r 02 dp2r (terminal) - (x) - (x) - (x) - (x) dp23 (x) dp22 (x) dp21 (x) dp20 (x) r 03 dp0r (latch) dp07 (1) dp06 (1) dp05 (1) dp04 (1) dp03 (1) dp02 (1) dp01 (1) dp00 (1) rw 04 dp1r (latch) - (x) - (x) - (x) - (x) dp13 (1) dp12 (1) dp11 (1) dp10 (1) rw 05 dp2r (latch) - (x) - (x) - (x) - (x) dp23 (1) dp22 (1) dp21 (1) dp20 (1) rw 10 pwm0 - (x) pwm06 (0) pwm05 (0) pwm04 (0) pwm03 (0) pwm02 (0) pwm01 (0) pwm00 (0) rw 11 pwm1 - (x) pwm16 (0) pwm15 (0) pwm14 (0) pwm13 (0) pwm12 (0) pwm11 (0) pwm10 (0) rw 12 pwm2 - (x) pwm26 (0) pwm25 (0) pwm24 (0) pwm23 (0) pwm22 (0) pwm21 (0) pwm20 (0) rw 13 pwm3 - (x) pwm36 (0) pwm35 (0) pwm34 (0) pwm33 (0) pwm32 (0) pwm31 (0) pwm30 (0) rw 14 pwm4 - (x) - (x) pwm45 (0) pwm44 (0) pwm43 (0) pwm42 (0) pwm41 (0) pwm40 (0) rw 15 pwm5 - (x) - (x) pwm55 (0) pwm54 (0) pwm53 (0) pwm52 (0) pwm51 (0) pwm50 (0) rw 16 pwm6 - (x) - (x) pwm65 (0) pwm64 (0) pwm63 (0) pwm62 (0) pwm61 (0) pwm60 (0) rw 17 pwm7 - (x) - (x) pwm75 (0) pwm74 (0) pwm73 (0) pwm72 (0) pwm71 (0) pwm70 (0) rw 18 vstl - (x) vst06 (0) vst05 (0) vst04 (0) vst03 (0) vst02 (0) vst01 (0) vst00 (0) rw 19 vsth - (x) vst13 (0) vst12 (0) vst11 (0) vst10 (0) vst09 (0) vst08 (0) vst07 (0) rw 20 afccn - (x) afch1 (0) afch0 (0) afcv3 (0) afcv2 (0) afcv1 (0) afcv0 (0) afcc (1) (x) rw 21 pwme pwm7e (0) pwm6e (0) pwm5e (0) pwm4e (0) pwm3e (0) pwm2e (0) pwm1e (0) pwm0e (0) rw 22 con1 tdace (0) scle (0) sdae (0) afce2 (0) afce1 (0) afce0 (0) vow1e (0) vow0e (0) rw 23 con2 vint (0) vien (0) - (x) - (x) - (x) p14lvl (0) p7lvl (0) p6lvl (0) rw
1995 jun 15 60 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 note 1. this bit is read only. 24 t3con t3b7 (0) t3b6 (0) t3b5 (0) t3b4 (0) t3b3 (0) t3b2 (0) t3b1 (0) t3b0 (0) r 25 pllcn - (x) pll6 (0) pll5 (0) pll4 (0) pll3 (0) pll2 (0) pll1 (0) pll0 (0) rw 30 dcrar - (x) - (x) dcra5 (0) dcra4 (0) dcra3 (0) dcra2 (0) dcra1 (0) dcra0 (0) rw 31 dcrtr - (x) - (x) - (x) - (x) dcrt3 (1) dcrt2 (1) dcrt1 (1) dcrt0 (1) w 32 dcrcr - (x) - (x) dcrc5 (1) dcrc4 (1) dcrc3 (1) dcrc2 (1) dcrc1 (1) dcrc0 (1) w 33 con3 - (x) - (x) - (x) - (x) br1 (0) br0 (0) bf1 (1) bf0 (1) rw 34 con4 - (x) - (x) s1 (0) s0 (0) hp (0) vp (0) bp (1) en (0) rw 35 vpos - (x) - (x) v5 (1) v4 (1) v3 (1) v2 (1) v1 (1) v0 (1) w 36 hpos - (x) - (x) h5 (0) h4 (0) h3 (0) h2 (0) h1 (0) h0 (0) w 37 bcc - (x) - (x) - (x) - (x) - (x) bcr (0) bcg (0) bcb (1) w addr (hex) reg76543210r/w
1995 jun 15 61 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 18 input/output there are 3 different port options available for the port pins in the 84cxxx derivatives (see figs 47, 48 and 49). each i/o port line may be individually configured using one of three mask options. the three i/o mask options are specified below: option 1 standard input/output with switched pull-up current source; this is shown in fig.47. option 1 input/output with open drain output; this is shown in fig.48. option 2 push-pull output; this is shown in fig.49. the state of each output port after a power-on-reset can also be selected using the mask options. all port mask options are given in section 19.1. the output stage consists of 4 transistors: tr1: n - channel transistor for sink tr2: p - channel transistor for boost-up tr3: p - channel transistor for pull-up tr4: p - channel transistor for constant current. see tables 41 and 42 for possible port option list. fig.47 standard output with switched pull-up current source (option 1). handbook, full pagewidth dd mq sq sq data bus write pulse outl/orl/anl/mov in/mov orl/anl/mov i/o port line tr3 tr2 tr1 v 100 m a typical (v = 0.7 v ) med186 - 1 dd dd v ss master slave o
1995 jun 15 62 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 fig.48 open drain output (option 2). handbook, full pagewidth dd mq sq data bus write pulse outl/orl/anl in v orl/anl i/o port line tr1 v med187 - 1 dd ss master slave fig.49 push-pull output (option 3). handbook, full pagewidth dd mq sq data bus write pulse outl/orl/anl in orl/anl i/o port line tr2 tr1 v med188 dd v ss master slave
1995 jun 15 63 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 19 option lists 19.1 port option for the port options (1, 2 and 3) see figs 47, 48 and 49. table 41 port options for making piggyback only the port pins whose options are left blank, e.g. dp00, can be user mask programmable. notes 1. s = set (and r = reset), initial h or l after power-on reset. 2. option 2 or 3 only (i.e. output only). table 42 port options for production only the port pins whose options are left blank, e.g. dp00, can be user mask programmable. notes 1. s = set (and r = reset), initial h or l after power-on reset. 2. option 2 or 3 only (i.e. output only). 19.2 on-chip oscillator transconductance port pin option port/dport pin option dport pin option dport pin option p00 13 1 s (1) p10 7 1 s dp00 29 dp20 40 2 s p01 14 1 s p11 8 1 s dp01 28 dp21 39 2 s p02 15 1 s p12 10 1 s dp02 27 dp22 3 p03 16 1 s p14 12 1 s dp03 26 dp23 4 p04 17 1 s dp10 38 dp04 25 p05 18 1 s dp11 37 dp05 24 p06 19 1 s dp12 36 dp06 23 vob (2) 1 p07 20 1 s dp13 9 dp07 22 vow2 (2) 2 port pin option port/dport pin option dport pin option dport pin option p00 13 p10 7 dp00 29 dp20 40 2 s (1) p01 14 p11 8 dp01 28 dp21 39 2 s p02 15 p12 10 dp02 27 dp22 3 p03 16 p14 12 dp03 26 dp23 4 p04 17 dp10 38 dp04 25 p05 18 dp11 37 dp05 24 p06 19 dp12 36 dp06 23 vob (2) 1 p07 20 dp13 9 dp07 22 vow2 (2) 2 option typ. g m at 5 v f osc for quartz f osc for pxe low (g ml ) 0.4 ms 1 to 6 mhz not allowed medium (g mm ) 1.6 ms 4 to 10 mhz 1 to 6 mhz high (g mh ) 4.5 ms not allowed 3 to 10 mhz
1995 jun 15 64 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 20 limiting values in accordance with the absolute maximum rating system (iec 134) 21 dc characteristics v dd =5v;v ss =0v;t amb = - 20 to +70 c; all voltages with respect to v ss ; unless otherwise speci?ed. symbol parameter min. max. unit v dd supply voltage - 0.3 +7 v v i all input voltages - 0.3 v dd + 0.3 v p tot total power dissipation - 1w i oh maximum source current for all port lines -- 10 ma i ol maximum sink current for all port lines - 30 ma t stg storage temperature - 55 +125 c t amb ambient operating temperature - 20 +70 c symbol parameter conditions min. typ. max. unit v dd operating supply voltage 4.5 5.0 5.5 v i dd operating supply current f osd(rc) , f osd(lc) =f xtal f xtal =10mhz - 510ma f xtal = 6 mhz - 3.5 7 ma f osd(rc) , f osd(lc) = stop f xtal =10mhz - 36ma f xtal = 6 mhz - 1.5 4 ma input ports p00, p01, dp00, dp01 and dp02 v il low level input voltage v dd = 4.5 v to 5.5 v 0 - 0.3v dd v v ih high level input voltage v dd = 4.5 v to 5.5 v 0.7v dd - v dd v i li input leakage current v dd = 4.5 v to 5.5 v; v ss < v i < v dd -- 10 m a output port p00 v ol low level output voltage i ol =10ma -- 1.2 v i oh high level pull-up output source current v o = 0.7v dd - 40 - 100 -m a high level pull-up output source current v o =v ss -- 140 - 400 m a high level push-pull output source current v o =v dd - 0.4 v - 3.0 - 7.0 - ma dp00/pwm00 to dp07/pwm07 as derivative port i ol low level output sink current v ol = 0.4 v 5.0 12.0 - ma i oh high level pull-up output source current v o = 0.7v dd - 40 - 100 -m a high level pull-up output source current v o =v ss -- 140 - 400 m a high level push-pull output source current v o =v dd - 0.4 v - 3.0 - 7.0 - ma
1995 jun 15 65 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 dp00/pwm00 to dp07/pwm07 as pwm output port i ol low level output sink current v ol = 0.4 v 0.7 1.5 - ma i oh high level pull-up output source current v o = 0.7v dd - 40 - 100 -m a high level pull-up output source current v o =v ss -- 140 - 400 m a high level push-pull output source current v o =v dd - 0.4 v - 0.7 - 1.5 - ma port p10 to p13 outputs i ol low level output sink current v ol = 0.4 v 5.0 12.0 - ma i oh high level pull-up output source current v o = 0.7v dd - 40 - 100 -m a high level pull-up output source current v o =v ss -- 140 - 400 m a high level push-pull output source current v o =v dd - 0.4 v - 3.0 - 7.0 - ma outputs vob and vow2 i ol low level output sink current v ol = 0.4 v 1.4 3.0 - ma i oh high level pull-up output source current v o = 0.7v dd - 40 - 100 -m a high level pull-up output source current v o =v ss -- 140 - 400 m a high level push-pull output source current v o =v dd - 0.4 v - 1.4 - 3 - ma dp10/afc0, dp11/afc1 and dp12/afc2 as derivative output port i ol low level output sink current v ol = 0.4 v 5.0 12.0 - ma i oh high level pull-up output source current v o = 0.7v dd - 40 - 100 -m a high level pull-up output source current v o =v ss -- 140 - 400 m a high level push-pull output source current v o =v dd - 0.4 v - 3.0 - 7.0 - ma dp20/sda and dp21/scl outputs i ol low level output sink current v ol = 0.4 v 3.0 -- ma i oh high level pull-up output source current v o = 0.7v dd - 40 - 100 -m a high level pull-up output source current v o =v ss -- 140 - 400 m a high level push-pull output source current v o =v dd - 0.4 v -- 7.0 - ma dp22/vow1, dp23/vow0 and dp13/tdac as derivative output port i ol low level output sink current v ol = 0.4 v 5.0 12.0 - ma i oh high level pull-up output source current v o = 0.7v dd - 40 - 100 -m a high level pull-up output source current v o =v ss -- 140 - 400 m a high level push-pull output source current v o =v dd - 0.4 v - 3.0 - 7.0 - ma dp22/vow1 and dp23/vow0 as vowi output i ol low level output sink current v ol = 0.4 v 1.4 3.0 - ma i oh high level pull-up output source current v o = 0.7v dd - 40 - 100 -m a high level pull-up output source current v o =v ss -- 140 - 400 m a high level push-pull output source current v o =v dd - 0.4 v - 1.4 - 3.0 - ma symbol parameter conditions min. typ. max. unit
1995 jun 15 66 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 22 ac characteristics v dd =5v;t amb = - 20 to +70 c; all voltages with respect to v ss ; unless otherwise speci?ed. note 1. oscillator with three (3) options for optimum use. 23 afc characteristics dp13/tdac as tdac output i ol low level output sink current v ol = 0.4 v 1.4 3.0 - ma i oh high level pull-up output source current v o = 0.7v dd - 40 - 100 -m a high level pull-up output source current v o =v ss -- 140 - 400 m a high level push-pull output source current v o =v dd - 0.4 v - 1.4 - 3.0 - ma emu/test, reset, int/t0, t1, hsync, vsync and t3 (schmitt-trigger input) v il low level input voltage v dd = 4.5 v to 5.5 v 0 - 0.3v dd v v ih high level input voltage v dd = 4.5 v to 5.5 v 0.7v dd - v dd v i li input leakage current v dd = 4.5 v to 5.5 v; v ss < v i < v dd - 1.0 - +1.0 m a symbol parameter conditions min. typ. max. unit oscillator f xtal crystal frequency (note 1) 1 - 10.0 mhz f osc-xtal oscillator frequency; option 1 g m = 0.4 ms (typ.) 1 - 6.0 mhz f osc-pxe not allowed mhz f osc-xtal oscillator frequency; option 2 g m = 1.6 ms (typ.) 4.0 - 10.0 mhz f osc-pxe 1.0 - 6.0 mhz f osc-xtal oscillator frequency; option 3 g m = 4.5 ms (typ.) not allowed mhz f osc-pxe 3.0 - 10.0 mhz c xtal1 external capacitance at xtal1 with xtal resonator not required pf with pxe resonator - 30 100 pf c xtal2 external capacitance at xtal2 with xtal resonator not required pf with pxe resonator - 30 100 pf f osd osd clock frequency 4.0 8.0 12.0 mhz symbol parameter min. typ. max. unit t afc conversion time (from any change in the afc: channel number, voltage level, enable/disable) with f xtal =10mhz -- 7 m s dp10/afc0, dp11/afc1 and dp12/afc2 comparator input v ai comparator analog input voltage v ss - v dd v v ae conversion error range -- 0.5 lsb symbol parameter conditions min. typ. max. unit
1995 jun 15 67 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 24 package outline unit b 1 cee m h l references outline version european projection issue date iec jedec eiaj mm dimensions (mm are the original dimensions) sot270-1 90-02-13 95-02-04 b max. w m e e 1 1.3 0.8 0.53 0.40 0.32 0.23 38.9 38.4 14.0 13.7 3.2 2.9 0.18 1.778 15.24 15.80 15.24 17.15 15.90 1.73 5.08 0.51 4.0 m h c (e ) 1 m e a l seating plane a 1 w m b 1 e d a 2 z 42 1 22 21 b e pin 1 index 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. (1) (1) d (1) z a max. 12 a min. a max. sdip42: plastic shrink dual in-line package; 42 leads (600 mil) sot270-1
1995 jun 15 68 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 25 soldering 25.1 introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). 25.2 soldering by dipping or by wave the maximum permissible temperature of the solder is 260 c; solder at this temperature must not be in contact with the joint for more than 5 seconds. the total contact time of successive solder waves must not exceed 5 seconds. the device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified storage maximum (t stg max ). if the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 25.3 repairing soldered joints apply a low voltage soldering iron (less than 24 v) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. if the temperature of the soldering iron bit is less than 300 c it may remain in contact for up to 10 seconds. if the bit temperature is between 300 and 400 c, contact may be up to 5 seconds.
1995 jun 15 69 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 26 definitions 27 life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. 28 purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
1995 jun 15 70 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 notes
1995 jun 15 71 philips semiconductors preliminary speci?cation microcontrollers for tv tuning control and osd applications PCA84C646; pca84c846 notes
philips semiconductors C a worldwide company argentina: ierod, av. juramento 1992 - 14.b, (1428) buenos aires, tel. (541)786 7633, fax. (541)786 9367 australia: 34 waterloo road, north ryde, nsw 2113, tel. (02)805 4455, fax. (02)805 4466 austria: triester str. 64, a-1101 wien, p.o. box 213, tel. (01)60 101-1236, fax. (01)60 101-1211 belgium: postbus 90050, 5600 pb eindhoven, the netherlands, tel. (31)40 783 749, fax. (31)40 788 399 brazil: rua do rocio 220 - 5 th floor, suite 51, cep: 04552-903-s?o paulo-sp, brazil. p.o. box 7383 (01064-970), tel. (011)821-2333, fax. (011)829-1849 canada: philips semiconductors/components: tel. (800) 234-7381, fax. (708) 296-8556 chile: av. santa maria 0760, santiago, tel. (02)773 816, fax. (02)777 6730 colombia: iprelenso ltda, carrera 21 no. 56-17, 77621 bogota, tel. (571)249 7624/(571)217 4609, fax. (571)217 4549 denmark: prags boulevard 80, pb 1919, dk-2300 copenhagen s, tel. (032)88 2636, fax. (031)57 1949 finland: sinikalliontie 3, fin-02630 espoo, tel. (358)0-615 800, fax. (358)0-61580 920 france: 4 rue du port-aux-vins, bp317, 92156 suresnes cedex, tel. (01)4099 6161, fax. (01)4099 6427 germany: p.o. box 10 63 23, 20043 hamburg, tel. (040)3296-0, fax. (040)3296 213. greece: no. 15, 25th march street, gr 17778 tavros, tel. (01)4894 339/4894 911, fax. (01)4814 240 hong kong: philips hong kong ltd., 15/f philips ind. bldg., 24-28 kung yip st., kwai chung, n.t., tel. (852)424 5121, fax. (852)480 6960/480 6009 india: philips india ltd, shivsagar estate, a block , dr. annie besant rd. worli, bombay 400 018 tel. (022)4938 541, fax. (022)4938 722 indonesia: philips house, jalan h.r. rasuna said kav. 3-4, p.o. box 4252, jakarta 12950, tel. (021)5201 122, fax. (021)5205 189 ireland: newstead, clonskeagh, dublin 14, tel. (01)7640 000, fax. (01)7640 200 italy: philips semiconductors s.r.l., piazza iv novembre 3, 20124 milano, tel. (0039)2 6752 2531, fax. (0039)2 6752 2557 japan: philips bldg 13-37, kohnan 2 -chome, minato-ku, tokyo 108, tel. (03)3740 5130, fax. (03)3740 5077 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. (02)709-1412, fax. (02)709-1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. (03)750 5214, fax. (03)757 4880 mexico: 5900 gateway east, suite 200, el paso, tx 79905, tel. 9-5(800)234-7381, fax. (708)296-8556 netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb tel. (040)783749, fax. (040)788399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. (09)849-4160, fax. (09)849-7811 norway: box 1, manglerud 0612, oslo, tel. (022)74 8000, fax. (022)74 8341 pakistan: philips electrical industries of pakistan ltd., exchange bldg. st-2/a, block 9, kda scheme 5, clifton, karachi 75600, tel. (021)587 4641-49, fax. (021)577035/5874546 philippines: philips semiconductors philippines inc, 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. (02)810 0161, fax. (02)817 3474 portugal: philips portuguesa, s.a., rua dr. antnio loureiro borges 5, arquiparque - miraflores, apartado 300, 2795 linda-a-velha, tel. (01)4163160/4163333, fax. (01)4163174/4163366 singapore: lorong 1, toa payoh, singapore 1231, tel. (65)350 2000, fax. (65)251 6500 south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430, johannesburg 2000, tel. (011)470-5911, fax. (011)470-5494. spain: balmes 22, 08007 barcelona, tel. (03)301 6312, fax. (03)301 42 43 sweden: kottbygatan 7, akalla. s-164 85 stockholm, tel. (0)8-632 2000, fax. (0)8-632 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. (01)488 2211, fax. (01)481 77 30 taiwan: philips taiwan ltd., 23-30f, 66, chung hsiao west road, sec. 1. taipeh, taiwan roc, p.o. box 22978, taipei 100, tel. (02)388 7666, fax. (02)382 4382 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, thailand, tel. (662)398-0141, fax. (662)398-3319 turkey: talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. (0 212)279 27 70, fax. (0212)282 67 07 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. (0181)730-5000, fax. (0181)754-8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. (800)234-7381, fax. (708)296-8556 uruguay: coronel mora 433, montevideo, tel. (02)70-4044, fax. (02)92 0601 internet: http://www.semiconductors.philips.com/ps/ for all other countries apply to: philips semiconductors, international marketing and sales, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, telex 35000 phtcnl, fax. +31-40-724825 scd40 ? philips electronics n.v. 1995 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. printed in the netherlands 453061/1500/03/pp72 date of release: 1995 jun 15 document order number: 9397 750 00166

▲Up To Search▲

Price & Availability of PCA84C646

	To Download PCA84C646 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .